A Study on the Performance Modeling of Input-Buffered Multistage Interconnection Networks Under a Nonuniform Traffic Pattern with Small Clock Cycle Schemes

Mun Youngsong

A Study on the Performance Modeling of Input-Buffered Multistage Interconnection Networks Under a Nonuniform Traffic Pattern with Small Clock Cycle Schemes

Mun Youngsong, Journal of Internet Computing and Services, Vol. 5, No. 4, pp. 35-42, Aug. 2004
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Keywords: Multistage Interconnection Networks, Nonuniform Traffic, Small Clock Cycle

Abstract

In this paper the more accurate models than any other ones so far have been proposed for the performance evaluation of single-buffered banyan-type Multistage Interconnection Networks(MINs)'s under nonuniform traffic condition is obtained. Small clock cycle instead of big clock cycle is used. The accuracy of proposed models are conformed by comparing with the results from simulation.

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Cite this article

[APA Style]

Youngsong, M. (2004). A Study on the Performance Modeling of Input-Buffered Multistage Interconnection Networks Under a Nonuniform Traffic Pattern with Small Clock Cycle Schemes. Journal of Internet Computing and Services, 5(4), 35-42.

[IEEE Style]

M. Youngsong, "A Study on the Performance Modeling of Input-Buffered Multistage Interconnection Networks Under a Nonuniform Traffic Pattern with Small Clock Cycle Schemes," Journal of Internet Computing and Services, vol. 5, no. 4, pp. 35-42, 2004.

[ACM Style]

Mun Youngsong. 2004. A Study on the Performance Modeling of Input-Buffered Multistage Interconnection Networks Under a Nonuniform Traffic Pattern with Small Clock Cycle Schemes. Journal of Internet Computing and Services, 5, 4, (2004), 35-42.